Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional DLL. DLL 100 generally comprises a phase detector (PD) 102, a charge pump 104, a loop filter 106, and a delay line 108 (which includes a set of buffers 110-1 to 110-n). In operation, DLL 100 is supposed to lock so that total delay D of the delay line 108 is approximately equal to period of the reference clock signal REF. Lock is achieved with the help of PD 102; however, PD 102 is generally limited to operating under the condition that the delay D is between 0 and twice the period of the reference clock signal REF. If delay D is outside of this range, DLL 100 can potentially to lock to other multiples of the period of the reference clock signal REF (harmonic lock) and can cause functional failure. Thus, there is a need for a circuit to generally ensure that the delay remains in a predetermined range.
An example of another conventional DLL is U.S. Pat. No. 6,977,605.